You can create custom condition symbols targeted to a top-level FPGA VI and use these symbols in any Disable Structure within your FPGA application.
Before you begin, you must designate a top-level FPGA VI in your application. Refer to Designating a Top-Level FPGA VI for more information.
In SystemDesigner, select the top-level FPGA VI in your application.
On the Item tab, in the Compile Symbols section, click the plus button to create a new symbol.
Enter a name and value for the symbol. Choose a name that indicates what the condition symbol is evaluating.
You can now select the symbol you created in a
in any document in your application.