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Using Clock Domains to Control the Execution Rate of an FPGA VI

Last Modified: September 20, 2016

FPGA targets support more than one clock. By configuring each Clock-Driven Loop to use a different clock, you can implement multiple clock domains in an FPGA VI to execute your code at different rates to achieve separate timing objectives within one application.

What to Use

What to Do

Create the following diagram to implement clock domains that control the execution rates of code within Clock-Driven Loops.

Customize the gray sections for your unique programming goals.

Divide your code into sections according to the separate timing objectives of your application. Place each section inside a Clock-Driven Loop.
When you wire a clock to the Clock-Driven Loop, all code placed within the loop attempts to execute within one clock cycle of the chosen clock. For each Clock-Driven Loop on your diagram, select a clock that allows you to execute code at a rate that meets your timing objective for that section of code.
spd-note-note
Note  

To execute more than one Clock-Driven Loop at the same clock rate, wire a single clock constant to multiple loops.

spd-note-tip
Tip  

If you want to create modular code for use with different clocks in different applications, wire a clock control to the Clock-Driven Loop instead of a clock constant.

Troubleshooting

If your code fails to meet the timing objectives of your application using the clocks you choose, create derived clocks to run code at frequencies that are not available as base clocks.

Examples

Search LabVIEW for the following installed examples: Multiple Clock Domains


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