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Compiling a Bitfile to Run on the FPGA

Last Modified: April 26, 2016

To run code on an FPGA, you must compile the top-level FPGA VI and its referenced documents into a bitfile that you then deploy to the FPGA. The bitfile transfers all the code and performance requirements of an application to an FPGA target.

Complete the following steps to begin compiling a bitfile:

  1. In SystemDesigner, select the top-level FPGA VI for your application. When you designate a bitfile build output for a VI, LabVIEW recognizes the VI as the top-level FPGA VI.
  2. In the Item tab, click Build. The bitfile begins compiling immediately. The Compile Queue tab opens to show the status of current and completed compilations.
    spd-note-
    Warning  

    Do not change any code in your FPGA VI during the diagram analysis stage of compilation. Any changes you make to code during the diagram analysis stage may be reflected in the bitfile. If you want to continue working on code while you wait for the compilation to finish, do so after the diagram analysis stage.

Monitor the compilation of your bitfile to determine whether you need to make changes to your code.

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