Table Of Contents

Register Bus Nodes (G Dataflow)

Last Modified: September 9, 2016

Send register read and write instructions from your application on the host to the FPGA.

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Destroys the session to the Register Bus nodes.
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Returns a reference to the FPGA node that is associated with this session of the Register Bus nodes.
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Returns the depth, in elements, of the host memory part of the Host to Target DMA FIFO that transfers instructions from this instance of the Register Bus Host node to the corresponding FPGA node. You can set the depth of the instruction FIFO using the Set Instruction FIFO Depth node of this library.
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Opens a session to a host VI that can communicate with a corresponding node on the FPGA VI specified by the fpga ref parameter.
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Sends a register read instruction to the FPGA and returns the data from the read operation.
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Sends multiple register read instructions to the FPGA and returns the data from all the read operations in an array.
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Resets the host session and the host VI to which this session is connected. This node does not change the current settings for the Instruction FIFO Depth.
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Sets the depth, in elements, of the host memory part of the Host to Target DMA FIFO used to transfer instructions from a host node to a corresponding FPGA node.
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Sends a register write instruction to the FPGA.
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Sends multiple register write instructions to the FPGA.

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