Use the external HDL IP document to import third-party HDL IP for FPGA applications.
This IP can be in the form of HDL related source files, such as VHDL, or files that conform to the IP-XACT standard. Once you've imported the IP, you can use the IP within Clock-Driven Logic in an FPGA design.
The following image provides information about different areas in the EIP document.
- Import—Import files conforming to the IP-XACT standard (IEEE 1685), such as IP generated by Xilinx Vivado.
- Parse and Verify—Parse the ports from the IP source files and import various configurations such as the signals, Clock, Reset, and Enable. If configured correctly, this function is not needed for importing files already in the IP-XACT format.
- Main Synthesis Entity—This will be the top-level IP source file used for synthesis.
- Main Simulation Entity—This will be the top-level simulation file for your IP.
- Browse Files—Use these buttons to browse to the top-level files you want to include for the Main Synthesis Entity and the Main Simulation Entity.
- Additional Resources—Include additional synthesis and simulation files, as needed, for your design.
- Signal Configuration—Once the IP has been successfully imported through the Parse and Verify or Import selections, these fields will populate based on your design. Select each signal and configure options in the Item tab as needed.
- Generics—These are the Generics defined in the IP. Set the default value in the Item tab.
- Clock Configuration—Clocks from your design will be included here. Select the clock and configure options in the Item tab as needed.
- Required MMCMs and BUFGs—Declare the number of MMCMs and BUFGs used in the IP. This can be used to report errors at compile time if the design requires more MMCMs and BUFGs than the hardware can provide.
Refer to the
tab in the software for examples that demonstrate importing external HDL IP. These can be found under the path