Table Of Contents

Synchronize Signal Bus (Clock-Driven Logic)

Last Modified: September 10, 2016

Synchronously realizes a signal. If this target is the master, it distributes edge on the specified FPGA I/O line on the next falling edge of the CPTR when edge is high. If this target is not the master, it will ignore edge. All targets, master or otherwise, also read the FPGA I/O line. The synchronized edgeoutput goes high on the next CPTR edge after the edge is read from the FPGA I/O line.

spd-note-note
Note  

The input edge should be a pulse. This is enforced by the node. There is a rising edge detector in the edge input. Additionally, after an edge is seen, another edge is not recognized until after the edge distribution completes. This means that the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is seen within the CPTR period. Two physical connection topologies, bus and star, are supported. In the bus topology, all targets are connected to a common bus, usually the AUX I/O. In the star topology, the master is connected to all the slaves, usually with PPS TRIG, and also back to itself.

connector_pane_image
datatype_icon

sync.fpga io

The FPGA I/O line to send and receive the synchronization signals on. This line is commonly an AUX I/O line.

datatype_icon

synchronization delay

The number of clock cycles of delay that were added by synchronizing the input edge. This value is zero if enable is FALSE. If enable is TRUE, this value is valid only on the master target.

datatype_icon

synchronized edge

The synchronized input edge if enable is TRUE.

datatype_icon

sync.resources 2

The same instance that was passed in for sync.resources.

datatype_icon

sync.resources

The synchronization instance. sync.resources is obtained from the Create node.

datatype_icon

enable

A Boolean that specifies whether to synchronize the input edge or not.

spd-note-note
Note  

The sync.fpga io is floating until a target is specified as the master. enable should be FALSE until after the host Synchronization edit executes to prevent erroneous outputs on synchronized edge.

datatype_icon

edge

The input being synchronized. Because the first block this input encounters is a rising edge detector, the input signal edge is treated as a pulse.

Where This Node Can Run:

Desktop OS: none

FPGA:

All devices


Recently Viewed Topics