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Synchronize over PPS Trig (Clock-Driven Logic)

Last Modified: September 10, 2016

Synchronizes NI 294x/295x devices over the PPS Trig lines. Input Parameters clock x2 is used by the measurement logic as the measurement clock. This clock must run at twice the rate of the FPGA Clock, which is the clock that drives the Single Cycle Timed Loop (SCTL) that this VI is in. This clock must also derive from the FPGA Clock, so that it has a fixed phase relationship. This clock is commonly Data Clock x2. common reference is used by the measurement logic as the "start" signal. sync.resources identifies the Synchronization instance. 'sync.resources' is obtained from the Create VI of this library. enable specifies whether to synchronize the input 'edge' or not. Note: The 'sync.fpga io' may be floating until a target is specified as the master. 'enable' should be FALSE until after the host Synchronization VI executes to prevent erroneous outputs on 'synchronized edge'. edge is the input being synchronized. Because the first block this input encounters is a rising edge detector, the input signal 'edge' is treated as a pulse. sync.fpga io are the FPGA I/O lines to send and receive the synchronization signals on. Output Parameters sync.resources is the same instance that was passed in for 'sync.resources'. synchronization delay is the number of clock cycles of delay that were added by synchronizing the input 'edge'. This value is zero if 'enable' is false. If 'enable' is true, this value is valid only on the master target. synchronized edge is the synchronized input edge if 'enable' is true.

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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