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Using Handshaking to Ensure Valid Data in a Clock-Driven Loop

Last Modified: September 20, 2016

Clock-Driven Loops force nodes to return data every clock cycle. However, some nodes, called multi-cycle nodes, need more than one cycle to compute a valid result. Therefore, nodes that depend on data from multi-cycle nodes must know whether that data is valid. Use a handshaking protocol so that nodes in a Clock-Driven Loop communicate with one another to verify that transferred data is valid every clock cycle.

What to Use

  • Clock-Driven Loop in a G VI document targeted to an FPGA
  • Feedback Node (Reverse)
  • Nodes that support a handshaking protocol
    spd-note-note
    Note  

    Nodes that support a handshaking protocol include one or more of the following handshaking inputs or outputs: input valid, output valid, ready for input, and ready for output.

What to Do

Create the following diagram to ensure that nodes within a Clock-Driven Loop send and receive only valid data through each loop iteration.

Customize the gray sections for your unique programming goals.

Use a Data Exchange node or a terminal to connect the code in the Clock-Driven Loop to the rest of the system. Read FIFO in this diagram receives an array of data from a host VI and sends each sample sequentially to the downstream nodes in this code.

Use nodes from the Clock-Driven Logic palette to process the input data. All multi-cycle nodes from the Clock-Driven Logic palette have one or more of the following handshaking inputs or outputs: input valid, output valid, ready for input, and ready for output.

For all multi-cycle nodes, wire output valid of the upstream node to input valid of the downstream node, and wire ready for output of the downstream node through a Feedback Node to ready for input of the upstream node.

Use a Data Exchange node or a terminal to connect the code in the Clock-Driven Loop to the rest of the system. Write FIFO in this diagram transfers the data that is processed by the Clock-Driven Loop back to the Host VI in the order that the data is received.
Connect output valid of the upstream node with input valid of the downstream node to prevent the downstream node from accepting a new input until the upstream node produces a new valid result. When output valid is False, any data output from the node is undefined. The undefined value generated by a node may differ between simulation and hardware.
Use a Feedback Node to enable downstream nodes to communicate their readiness to receive a new input with upstream nodes. The Feedback Node sends the result from ready for input back to ready for output of an upstream node.

To avoid consuming an invalid input, each downstream node rejects new input data until both its ready for input produces a True value and its input valid receives a True value. Also, the upstream node sends new data only after the downstream node is ready for a new input, so the downstream node does not skip valid data.

Troubleshooting

  • If you receive unexpected or invalid output data, the handshaking signals may be wired incorrectly. For each upstream node, verify that output valid is wired to input valid of its adjacent downstream node. Also verify that, for each upstream node, ready for output is wired through a Feedback Node to ready for input of its adjacent downstream node.
  • If you are using FIFOs to communicate between the host VI and the target and receive unexpected data in the host VI, verify that the FIFO references in the FPGA VI match the FIFO references in the host VI. For more information about using FIFOs to transfer data between a host and target, see Transferring Data between a Host and Target Using FIFOs.

Examples

Search LabVIEW for the following installed examples:
  • FPGA Host Interface
  • FIFO
  • Multiple Clock Domains
Search LabVIEW for the following installed lessons:
  • Handshaking in Clock-Driven Logic
  • Programming with Clock-Driven Logic

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