Table Of Contents

Xilinx CORE Generator IP Nodes (Clock-Driven Logic)

Last Modified: September 9, 2016

node_icon
Implements channel estimation functionality for uplink LTE eNodeB applications based on the 3GPP TS 36.211 specification.
node_icon
Performs MIMO decoding using the MMSE algorithm.
node_icon
Implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 specification.
node_icon
Implements a high-speed, compact Turbo Encoder as defined in the 3GPP LTE specification.
node_icon
Implements a high-speed, compact Turbo Encoder as defined in the 3GPP specification.
node_icon
Generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input.
node_icon
Creates adders, subtracters, and adders/subtracters that operate on signed or unsigned data.
node_icon
Creates up counters, down counters, and up/down counters with output widths ranging up to 256 bits.
node_icon
Replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. Use this generator in all new Xilinx designs.
node_icon
Designs and implements Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices.
node_icon
Corrects color operations, such as white balance, color cast, brightness, or contrast in an RGB image.
node_icon
Reconstructs RGB data from color image sensors equipped with a Bayer Color Filter Array.
node_icon
Represents all operands and results as signed two's-complement data.
node_icon
Implements a high-speed, compact convolutional encoder with a puncturing option.
node_icon
Generates the generalized coordinate rotational digital computer (CORDIC) algorithm that iteratively solves trigonometric, hyperbolic, and square root equations.
node_icon
Provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores.
node_icon
Performs a discrete Fourier transform as defined by the LTE standard, in terms of point sizes, low latency, and resource requirements.
node_icon
Creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs.
node_icon
Provides division using the Radix-2 or High Radix algorithms.
node_icon
Allows you to specify multiple operations using arithmetic expressions you define to abstract the XtremeDSP Slice configuration and simplify its dynamic operation.
node_icon
Implements Digital Up Converters (DUCs) and Digital Down Converters (DDCs) for a range of wireless interface standards based on system-level parameters.
node_icon
Computes the Discrete Fourier Transform (DFT).
node_icon
Generates resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.
node_icon
Generates configurable high-speed, compact filter implementations.
node_icon
Provides a range of floating-point operations, such as addition, subtraction, multiplication, division, reciprocal, square-root, reciprocal-square-root, absolute value, logarithm, compare, and conversion operations.
node_icon
Manipulates pixel values.
node_icon
Provides edge enhancement of each frame of video data being processed.
node_icon
Implements either the Forney Convolutional or Rectangular Block type architecture.
node_icon
Provides an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v9.0.0 Multiplexing and channel coding specification.
node_icon
Implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidths.
node_icon
Implements the LTE Rach decoder function.
node_icon
Implements an AXI4 compliant, high-performance, optimized block for the 3GPP TS 36.212 v9.3.0 uplink shared channel.
node_icon
Generates parallel and constant-coefficient multipliers.
node_icon
Generates a multiply-add function implemented in XtremeDSPTM slices.
node_icon
Provides a flexible and highly efficient solution to reduce the peak to average power ratio (PAR) of complex multi-carrier waveforms.
node_icon
Generates fast, compact FIFO-style registers, delay lines, or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode.
node_icon
Implements many different Reed-Solomon coding standards.
node_icon
Implements many different Reed-Solomon coding standards.
node_icon
Provides built-in support for 5 formats and 3 range standards.
node_icon
Provides a video processing block for alpha blending and compositing as well as simple text and graphics generation.
node_icon
Spatially scales video streams in real time. It supports all SD and HD resolutions.
node_icon
Provides a general purpose video timing generator and detector.
node_icon
Implements a fully synchronous Viterbi decoder, using a single clock.
node_icon
Provides built-in support for 4 video standards and 3 input ranges.
node_icon
Provides the infrastructure to connect multiple AXI4-Stream masters and slaves.
node_icon
Provides the infrastructure to change the AXI4-Stream interface characteristics between an AXI4-Stream master and slave.
node_icon
Provides the infrastructure to insert a pipeline stage between an AXI4-Stream master and slave.
node_icon
Monitors AXI interfaces. When attached to an interface, this node actively checks for protocol violations and provides an indication of which violation occurred.
node_icon
Provides the infrastructure to change the data path width between an AXI4-Stream master and slave.
node_icon
Provides the infrastructure to insert buffering between an AXI4-Stream master and slave.
node_icon
Provides the ability to merge multiple SI streams onto one MI stream channel.
node_icon
Provides the ability to replicate one SI stream onto multiple MI stream channels.
node_icon
Provides an interface for controlling and synchronizing video frame stores from external memory.

Recently Viewed Topics