Table Of Contents

Write FIFO (Clock-Driven Logic)

Last Modified: September 10, 2016

Writes an element to an FPGA FIFO.

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reference in

A reference to a FIFO.

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data

The data element you would like to write to the FIFO. This data may be lost if the FIFO is full. Use ready for input or empty threshold met? to determine if data may safely be written to the FIFO.

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input valid

A Boolean that describes whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

TRUE The next data point has arrived for processing.
FALSE The next data point has not arrived for processing.
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reference out

A reference to a FIFO.

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ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
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Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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