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Request Data from DRAM (Clock-Driven Logic)

Last Modified: September 10, 2016

Queues requests for data from the DRAM memory on the FPGA target.

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reference in

Reference to a DRAM memory item.

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address

The location to write data in memory on the FPGA target. The valid address range depends on the requested number of elements you specify when creating the input memory item. For example, if you specify a requested number of elements of 65536, the valid address range is 0–65535. If address exceeds the address range, the data will not be written to memory.

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input valid

A Boolean that specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

TRUE The data point is valid and can be processed.
FALSE The data point is not valid.
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reference out

Reference to a DRAM memory item.

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ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
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Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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