Table Of Contents

Read FIFO (Clock-Driven Logic)

Last Modified: September 10, 2016

Reads and removes the oldest element from the FPGA FIFO.

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reference in

A reference to the FIFO to read from.

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ready for output

A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.
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Note  

If this input is False during a given cycle, output valid returns False during that cycle.

Default: TRUE

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reference out

A reference to the FIFO that was read from.

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data

The oldest data element in the FIFO. If the FIFO is empty, the returned element is undefined.

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output valid

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True The node has computed a result that downstream nodes can use.
False This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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