Table Of Contents

Peak Cancellation Crest Factor Reduction (Clock-Driven Logic)

Last Modified: September 10, 2016

Provides a flexible and highly efficient solution to reduce the peak to average power ratio (PAR) of complex multi-carrier waveforms.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

Interface: AXI4-Stream, AXI4-Lite

connector_pane_image

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


Recently Viewed Topics