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Multiply Adder (Clock-Driven Logic)

Last Modified: September 10, 2016

Generates a multiply-add function implemented in XtremeDSPTM slices.You can specify the word lengths of the inputs and output. In addition, pipelining for maximum speed and no pipelining are available.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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