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Interleaver/De-interleaver (Clock-Driven Logic)

Last Modified: September 10, 2016

Implements either the Forney Convolutional or Rectangular Block type architecture.For the Convolutional type, the number of branches and branch lengths are parameterizable. For the Rectangular Block type, the number of rows and columns are parameterizable or run-time variable. Row and column permutations are also supported. The core supports a symbol size ranging from 1 to 256 bits. The core incorporates Xilinx Smart-IP technology that is delivered through the Xilinx CORE Generator System and integrated seamlessly with the Xilinx design flow.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

Interface: AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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