Table Of Contents

High Throughput Rectangular to Polar (Clock-Driven Logic)

Last Modified: September 10, 2016

Converts rectangular coordinates to polar coordinates. This node returns the phase of the polar coordinates in pi radians, which use fewer FPGA resources than radians. To convert the phase into radians, divide the value by pi.

connector_pane_image
datatype_icon

x

X value of the rectangular coordinates.

This input supports only scalar values of the fixed-point data type.

spd-note-note
Note  

If you wire an unsigned value to this terminal that has a word length of 64 bits, LabVIEW coerces the word length to be 63 bits and displays a coercion dot on the wire.

x and y Coercion

If you wire fixed-point data types with different configurations to the inputs, this node uses a shared, signed fixed-point data type to represent the value of both inputs internally. The maximum word length of this internal data type is 64 bits. If the configurations of the inputs result in an internal word length greater than 64 bits, this node rounds off the fractional bits of one input to achieve an internal word length of 64 bits, resulting in a loss of precision. This node rounds off the input that has the most fractional bits.

datatype_icon

y

Y value of the rectangular coordinates.

This input supports only scalar values of the fixed-point data type.

spd-note-note
Note  

If you wire an unsigned value to this terminal that has a word length of 64 bits, LabVIEW coerces the word length to be 63 bits and displays a coercion dot on the wire.

x and y Coercion

If you wire fixed-point data types with different configurations to the inputs, this node uses a shared, signed fixed-point data type to represent the value of both inputs internally. The maximum word length of this internal data type is 64 bits. If the configurations of the inputs result in an internal word length greater than 64 bits, this node rounds off the fractional bits of one input to achieve an internal word length of 64 bits, resulting in a loss of precision. This node rounds off the input that has the most fractional bits.

datatype_icon

input valid

A Boolean that specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

TRUE The data point is valid and can be processed.
FALSE The data point is not valid.
datatype_icon

ready for output

A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.
spd-note-note
Note  

If this input is False during a given cycle, output valid returns False during that cycle.

Default: TRUE

datatype_icon

magnitude

Magnitude.

datatype_icon

phase

Phase in pi radians, which use fewer FPGA resources than radians. To convert this value into radians, divide phase by pi.

datatype_icon

output valid

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True The node has computed a result that downstream nodes can use.
False This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.
datatype_icon

ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
spd-note-note
Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Input Coercion

If you wire a fixed-point data type to only x or y, this node coerces the unwired input to match the configuration of the wired terminal.

spd-note-tip
Tip  

To create a second fixed-point data type with the same configuration as the wired input, right-click the unwired input and select Create»Control or Create»Constant.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


Recently Viewed Topics