A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
|True||The downstream node is ready for the next data point.|
|False||The downstream node is not ready for the next data point.|
Product of x and y.
A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
|True||The node has computed a result that downstream nodes can use.|
|False||This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.|
A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
|True||The node is ready to accept new input data.|
|False||The node is not ready to accept new input data.|
During the cycles before output valid returns True for the first time, this node might return different results on an FPGA target than on a host computer. The results become identical after the first time output valid returns True.
If you wire complex fixed-point data types to both inputs of High Throughput Multiply, you may experience a reduced clock rate at compile time. You may be able to increase the clock rate by increasing the number of Pipelining Stages for this node in the Item tab. If you cannot achieve your desired performance with pipelining, you can implement the same logic using Xilinx IP nodes.
You can improve the timing performance of this node on an FPGA target by adjusting the number of pipelining stages. The functionality of a pipelined multiplier is equivalent to a non-pipelined multiplier cascaded by a certain number of registers. The number of registers is equal to the number of pipelining stages.
In general, increasing the number of pipelining stages also increases the maximum clock rate this node can achieve. However, the actual clock rate depends on many considerations, including the following factors:
The following graphs show the number of Pipelining stages vs. maximum clock rate estimations on Xilinx Virtex-II, Virtex-5, and Spartan-3 FPGA targets, respectively.
In the previous figure, each line represents a multiplier of a certain size that uses a particular implementation resource. For example, the I32*I32 Block plot shows a multiplier that multiplies two 32-bit signed integers together by using an embedded block multiplier. The result is a signed 64-bit integer: I32<32.0> * I32<32.0> = I64<64.0>. If you use one pipelining stage on a Virtex-II FPGA target, this type of multiplier can achieve a maximum clock rate of about 51 MHz. If you use three pipelining stages, the maximum clock rate becomes about 76 MHz.
The following figures show similar information for other FPGA targets.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices