Table Of Contents

High Throughput Multiply (Clock-Driven Logic)

Last Modified: May 15, 2017

Computes the product of two specified values (x and y).This node supports a handshaking protocol.

connector_pane_image
datatype_icon

x

Multiplicand.

datatype_icon

y

Multiplicator.

datatype_icon

input valid

A Boolean that specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

TRUE The data point is valid and can be processed.
FALSE The data point is not valid.
datatype_icon

ready for output

A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.
spd-note-note
Note  

If this input is False during a given cycle, output valid returns False during that cycle.

Default: TRUE

datatype_icon

operation overflow

A Boolean that indicates whether the theoretical computed value exceeds the valid range of the output data type.

TRUE The theoretical computed value exceeds the valid range of the output data type.
FALSE The theoretical computed value does not exceed the valid range of the output data type.
datatype_icon

x*y

Product of x and y.

datatype_icon

output valid

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True The node has computed a result that downstream nodes can use.
False This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.
datatype_icon

ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
spd-note-note
Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Different Results between FPGA and Host Computer Deployments

During the cycles before output valid returns True for the first time, this node might return different results on an FPGA target than on a host computer. The results become identical after the first time output valid returns True.

Diminished Clock Rate with Complex Fixed-Point Data Types

If you wire complex fixed-point data types to both inputs of High Throughput Multiply, you may experience a reduced clock rate at compile time. You may be able to increase the clock rate by increasing the number of Pipelining Stages for this node in the Item tab. If you cannot achieve your desired performance with pipelining, you can implement the same logic using Xilinx IP nodes.

Improve Performance with Pipelining

You can improve the timing performance of this node on an FPGA target by adjusting the number of pipelining stages. The functionality of a pipelined multiplier is equivalent to a non-pipelined multiplier cascaded by a certain number of registers. The number of registers is equal to the number of pipelining stages.

In general, increasing the number of pipelining stages also increases the maximum clock rate this node can achieve. However, the actual clock rate depends on many considerations, including the following factors:

  • The FPGA target you use
  • The size of the multiplier
  • The rounding and overflow modes you select in the fixed-point configuration for the node
  • The Implementation resource you configure
  • Other FPGA logic besides the multiplier

The following graphs show the number of Pipelining stages vs. maximum clock rate estimations on Xilinx Virtex-II, Virtex-5, and Spartan-3 FPGA targets, respectively.

spd-note-note
Note  

NI obtained these estimates after synthesis and without considering the impact of the rounding mode, overflow mode, or routing. Therefore, the clock rate estimates might be higher than what you actually can achieve.

In the previous figure, each line represents a multiplier of a certain size that uses a particular implementation resource. For example, the I32*I32 Block plot shows a multiplier that multiplies two 32-bit signed integers together by using an embedded block multiplier. The result is a signed 64-bit integer: I32<32.0> * I32<32.0> = I64<64.0>. If you use one pipelining stage on a Virtex-II FPGA target, this type of multiplier can achieve a maximum clock rate of about 51 MHz. If you use three pipelining stages, the maximum clock rate becomes about 76 MHz.

The following figures show similar information for other FPGA targets.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


Recently Viewed Topics