Generates resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. The FIFO Generator provides a selection of memory resource types for implementation, such as a Hamming code-based error detection and correction as well as error injection capability for system test help to ensure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4, AXI4-Stream, AXI4-Lite
Where This Node Can Run:
Desktop OS: none
FPGA: All devices