Table Of Contents

Discrete Delay (Clock-Driven Logic)

Last Modified: September 10, 2016

Delays the input value by a specified value.This node supports scalar and array values of integer, fixed-point, and Boolean data types, clusters, and arrays of clusters.

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D

Data to delay.

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Note  

The data type of D does not adapt to source.

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n-1

Index of the internal register whose value reaches the Q output. The value of n-1 can be between 0 and n-1, where n is the value of Maximum Delay on the Item tab.

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initial values

Settings for the initial values of the internal registers this node uses.

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enable

A Boolean that indicates whether this node ignores the input to D.

TRUE This node shifts all values to the next internal register and takes in a value of D to the first internal register.
FALSE This node ignores D and does not shift existing values, which means the internal registers retain the value they had during the previous clock cycle.

Use this input to operate on only valid values of D. For example, you can wire the output valid output of High Throughput Math nodes to this input. In this situation, Discrete Delay takes in a value of D only if the incoming value is valid.

Default: TRUE

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Q

Delayed value of D. Q returns the value of the register you specify with the n-1 input.

Choosing between Discrete Delay and the Feedback Node

Discrete Delay and the Feedback Node are similar but have some key differences. The following table provides recommendations for choosing between the two nodes.

Feedback Node Discrete Delay Recommendation
Design and features Designed for
  • Feeding back output signals to an input.
  • Delaying an input signal by a constant number of clock cycles.
Designed for delaying an input signal by a constant or variable number of clock cycles. Use the node that represents the use case you are programming.
Initialization options Initialize internal registers to custom values in the following situations:
  • On first call to the FPGA VI or when the FPGA VI resets
  • When the FPGA VI compiles or loads or when the FPGA VI resets
  • When the FPGA VI compiles or loads, ignoring when the FPGA VI resets
  • Reset internal registers to zeroes on the first call to the FPGA VI or when the FPGA VI resets
  • Initialize internal registers to custom values when the FPGA VI compiles or loads, ignoring when the FPGA VI resets
Discrete Delay implements delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.
Ways of defining initial values You define initial values by wiring a value to the initial values input on the diagram. You define initial values by using the initial values input. Use Discrete Delay if you have an initialization VI or if you need to delay a fixed-size array.
Support for dynamic delay No Yes Use Discrete Delay if you need a dynamic delay.
Support for representing feedback on a block diagram Yes No Use the Feedback Node if you need to represent feedback on a block diagram.

Performance Impact of How This Node Implements Delays

This node implements delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.

Performance Impact on Simulation

This node can increase simulation run time significantly when you use it in conjunction with downloading, stopping, or running the FPGA VI.

If you set Maximum Delay to 20 clock cycles, the node creates 20 registers for storing values. A value you wire to D moves from register 0 to register 19 with each successive clock cycle. However, when you use n-1 to specify the number of a specific internal register, Q returns the value of that register instead of always returning the value of the last register. For example, if 17 clock cycles have elapsed, the value of D you sent during the first clock cycle is in register 16. If you wire a value of 16 to n-1 during the 18th clock cycle, the node returns this value. The value has been delayed for 17 clock cycles, not 20.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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