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Complex Multiplier (Clock-Driven Logic)

Last Modified: September 10, 2016

Represents all operands and results as signed two's-complement data. Operand widths and result widths are parameterizable. Operand widths up to 63 bits are supported.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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