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Clear FIFO (Clock-Driven Logic)

Last Modified: September 10, 2016

Clears a target-scoped or VI-defined FPGA FIFO.

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reference in

A reference to a FIFO.

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start

A Boolean that specifies whether the node attempts to clear the specified FIFO. Leave this input unwired if you only want to check the status of a previous clear operation.

True The node attempts to clear the specified FIFO. If a clear operation is already in progress, the node does nothing.
False The node does not attempt to clear the FIFO.
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reference out

A reference to a FIFO.

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done

A Boolean that indicates whether the clear operation is complete.

True No clear operation has happened or the previous clear operation is complete.
False The clear operation started or is currently in progress.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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