Table Of Contents

Block Memory Generator (Clock-Driven Logic)

Last Modified: September 10, 2016

Replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. Use this generator in all new Xilinx designs.The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores that can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, consult the data sheet.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4, AXI4-Lite

connector_pane_image

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


Recently Viewed Topics