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AXI4-Stream Combiner (Clock-Driven Logic)

Last Modified: September 10, 2016

Provides the ability to merge multiple SI streams onto one MI stream channel.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream

connector_pane_image

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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