Implements an adder-subtractor that operates on bit patterns. You can cascade and pipeline AddSub nodes to achieve higher throughput rates.
A Boolean that determines whether this node accounts for an additional least-significant bit (LSB).
|True||Adds one extra LSB to x + y when sub? is False. Computes x – y normally when sub? is True.|
|False||Subtracts one extra LSB from x – y when sub? is True. Computes x + y normally when sub? is False.|
A Boolean that determines whether this node ignores the value you wire to x.
|True||This node uses a value of 0 instead of the value you wire to x.|
|False||This node uses the value you wire to x.|
Use this Boolean to remove x from the expression this node calculates. For example, use this Boolean to return –y instead of x – y.
An input to this node. If y is a fixed-size Boolean array, the first array element represents the LSB and the last element represents the MSB.
This input supports scalar Boolean values and arrays of Boolean values.
A Boolean that indicates whether the data type of sum cannot represent the result of an unsigned addition operation.
|True||The data type of sum cannot represent the result of an unsigned addition operation.|
|False||The data type of sum cannot represent the result of an unsigned subtraction operation.|
In this situation, this node wraps the value of sum. If you cascade this node, you can use this output to specify whether a downstream node carries or borrows a value. To specify that a downstream node uses this value, wire carry-out/inverted borrow-out to the carry-in/inverted borrow-in input of the downstream node.
The result this node computes. The result depends on not only the values of x and y but also the values of any Boolean inputs. This node applies the Wrap overflow mode to sum in the following situations:
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application