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Accumulator (Clock-Driven Logic)

Last Modified: September 10, 2016

Generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input.Inputs range from 1 to 256 bits wide. Outputs range from 1 to 258 bits.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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