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3GPP Turbo Encoder (Clock-Driven Logic)

Last Modified: September 10, 2016

Implements a high-speed, compact Turbo Encoder as defined in the 3GPP specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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