Table Of Contents

Register Instruction Arbiter (Clock-Driven Logic)

Last Modified: September 9, 2016

Controls the flow of register instructions from different instances of the Register Bus FPGA nodes that may have the same destination subsystem.

Any subsystem that receives register instructions from separate instances of the Register Bus FPGA nodes must have this node preceding the subsystem's Registers node. Register Instruction Arbiter is designed to run in a clock-driven loop. This node implements instances for arbitrating from two to twelve register instructions. The instance supporting two incoming register instructions has the following parameters.

Input Parameters

  • reset specifies whether to clear any instructions waiting to be processed. The ready for input parameter returns FALSE for all ports, if the reset parameter is set to TRUE.
  • port 0 specifies a read or write register instruction. Wire this parameter to the register instruction parameter of the Process node of the Register Bus FPGA library.
  • port 0.subsystem specifies the destination subsystem for this register read or write operation.
  • port 0.address specifies the destination address in the specified subsystem for this register read or write operation.
  • port 0.data specifies the data to be written to the specified register for a write operation.
  • port 0.valid specifies whether there is a valid register read or write instruction in the cluster. Set this parameter to TRUE if there is a valid read or write instruction and FALSE if there is no valid read or write instruction.
  • port 0.read specifies whether the instruction is for reading from or writing to the specified register. Set this parameter to TRUE if there is an instruction for reading from the specified register and FALSE if there is an instruction for writing to the specified register.
  • port 1 specifies a read or write register instruction. Wire this parameter to the register instruction parameter of the Process node of the Register Bus FPGA library.
  • port 1.subsystem specifies the destination subsystem for this register read or write operation.
  • port 1.address specifies the destination address in the specified subsystem for this register read or write operation.
  • port 1.data specifies the data to be written to the specified register for a write operation.
  • port 1.valid specifies whether there is a valid register read or write instruction in the cluster. Set this parameter to TRUE if there is a valid read or write instruction and FALSE if there is no valid read or write instruction.
  • port 1.read specifies whether the instruction is for reading from or writing to the specified register. Set this parameter to TRUE if there is an instruction for reading from the specified register and FALSE if there is an instruction for writing to the specified register.
  • ready for output specifies whether the downstream nodes are ready for this node to return a new value. The default is TRUE.
    spd-note-note
    Note  

    If this parameter is set to FALSE during a given cycle, the output valid parameter returns FALSE during that cycle.

Output Parameters

  • register instr out returns the register instruction, which the arbiter allows the downstream nodes to process.
  • register instr out.subsystem returns the destination subsystem for this register read or write operation.
  • register instr out.address returns the destination address in the specified subsystem for this register read or write operation.
  • register instr out.data returns the data to be written to the specified register for a write operation.
  • register instr out.valid indicates whether there is a valid register read or write instruction in the cluster. This node is designed to work with a downstream node that wires FALSE to the ready for output parameter on the clock cycle immediately following the clock cycle where the register instr out.valid parameter returns TRUE. The register instruction is only valid for a single clock pulse.
  • register instr out.read indicates whether the instruction is for reading from or writing to the specified register. This parameter returns TRUE if there is an instruction for reading from the specified register and FALSE if there is an instruction for writing to the specified register.
  • active input returns a cluster in which each element indicates whether one of the input ports has a register instruction that is allowed through the arbiter and is being processed by downstream nodes. Only one of the fields in this cluster returns TRUE at any time. Wire this parameter to the active input parameter of Read Completion Demux.
  • active input.input 0 indicates whether port 0 has a register instruction being processed by downstream nodes.
  • active input.input 1 indicates whether port 1 has a register instruction being processed by downstream nodes.
  • ready for input returns a cluster in which each element indicates whether one of the input ports is ready to accept a new register instruction. If valid register instructions arrive at multiple ready ports on the same call to this node, the register instructions that are not allowed through to the output port of this node stored in feedback nodes. When a register instruction stored in a port's feedback node, the field indicating whether that port is ready returns FALSE. When the stored instruction is processed on a subsequent call to this node, this field is set to TRUE.
  • ready for input.ready for port 0 input indicates whether port 0 can receive and possibly store a new register instruction.
  • ready for input.ready for port 1 input indicates whether port 1 can receive and possibly store a new register instruction. If more than one port has a valid register instruction ready, either stored in that port's feedback node from a previous call to this node or provided during the current call to this node, the arbiter gives preference to a valid instruction on the port that provided the previous instruction. If the port that provided the previous instruction does not have a valid register instruction ready, the arbiter will iterate through the ports to find the next port with a valid register instruction. In the instances of this node that support three and four input ports, controls for port 2 and port 3 are added to the node's connector pane. For instances that support from five to twelve input ports, the additional ports are bundled into the remaining elements (cluster). In the instances of this node that support more than two input ports, the ready for input and active input parameters are clusters where the number of Boolean fields is equal to the number of input ports.
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Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
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Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
node_icon
Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.
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Controls the flow of register instructions from different instances of the Register Bus FPGA library that may have the same destination subsystem.

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