Table Of Contents

Process (Clock-Driven Logic)

Last Modified: September 10, 2016

Retrieves and decodes instructions from the host for reading and writing registers that are contained in the register banks of different subsystems on the FPGA, and controls the processing of each instruction. This node performs the following actions:

  1. Reads instructions that a corresponding Register resource on the host writes into a DMA FIFO. The FPGA and Host resources must use the same name for the DMA FIFO.
  2. Decodes the instruction from the FIFO on the FPGA to identify the subsystem containing the register, the address of the register within its subsystem, information about whether the operation is to read or write the register, and the data to be written if the operation is a write operation.

The output from this node is the decoded information about the register instruction, and it is designed to be consumed by the Register resource of another subsystem's FPGA library. The Process node does not read the next instruction from the DMA FIFO until it receives an indication that a subsystem has completed processing the current instruction. For register writes, the Register Bus nodes can request notification that the FPGA node has consumed an instruction by wiring TRUE to the wait until committed parameter on the Write Register node or Write Register Array node in the Register Bus nodes palette. When a notification is requested, the Register Bus FPGA nodes wait until the Register Bus host nodes acknowledge receipt of the notification before retrieving the next instruction. This communication ensures that notifications are never dropped, but it affects the rate at which instructions are consumed.

To get the best performance, request notifications only for critical instructions. Drop an instance of this node for each instance of the Register Bus that your application requires. Unique instances of the Register Bus FPGA resources must use separate, uniquely-named DMA FIFOs for sending instructions from the host to the FPGA. Certain parameters must be wired to controls or indicators on the top-level FPGA VI because they are used to return data to the Register Bus Host library. The Register Bus FPGA library and the Register Bus Host library implement a handshaking protocol to safely exchange data. This node is designed to be run in a Clock-Driven Loop.

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Note  

This version of the Register Bus FPGA library supports a maximum of eight instances with instance numbers 0 to 7, inclusive.

Input Parameters

  • reg.notify host.go rcvd specifies whether the Register Bus Host nodes read a value of TRUE on the reg.notify host.go parameter as part of the handshaking protocol between the host and FPGA. The default value is FALSE. The reg.notify host.go rcvd parameter is used only when the Register Bus host nodes request a notification by setting the wait until committed parameter to TRUE on its Write Register node or Write Register Array node. When the Register Bus FPGA nodes complete the write operation, the Process node sets the reg.notify host.go parameter to TRUE. The Register Bus host nodes wait until the node reads this value before setting the reg.notify host.go rcvd parameter to TRUE to tell the FPGA that it received the notification. Then, the Register Bus FPGA nodes set the reg.notify host.go parameter to FALSE, and finally, the Register Bus host nodes sets the reg.notify host.go rcvd parameter to FALSE to end the transaction between the host and the FPGA for this notification. The Register Bus FPGA library waits until the reg.notify host.go rcvd parameter is set to FALSE before processing the next register instruction. The reg.notify host.go rcvd parameter must be wired to a control on the top-level FPGA VI because the parameter must be accessible to the Register Bus host nodes from the Read/Write FPGA Control function. The control must have a predefined name based on the value passed to the bus instance input of Open Session. The format of the name is reg.notify host.go rcvd N, where N is the instance number of the Register Bus host nodes and Register Bus FPGA nodes. For example, if the name is reg.notify host.go rcvd 0, the instance number of this library is 0.
  • reg.reset specifies whether the state machine that controls the processing of register instructions is reset to the state where it is ready for a new register instruction. The state machine stays in this state until this parameter is set to FALSE. The reg.reset parameter must be wired to a control on the top-level FPGA VI because the parameter must be accessible to the Register Bus host nodes from Read/Write FPGA Control. The control must have a predefined name based on the value passed to the bus instance parameter of Open Session. The format of the name is reg.reset N, where N is the instance number of the Register Bus host nodes and Register Bus FPGA nodes. For example, if the name is reg.reset 0, the instance number of this library is 0.
  • reg.host instruction fifo specifies the DMA FIFO used to download register instructions to the device. The DMA FIFO must be instantiated in the LabVIEW project and must have a predefined name based on the value passed to the bus instance parameter of Open Session. The format of the name is reg.host instruction fifo N, where N is the instance number of the Register Bus host nodes and Register Bus FPGA nodes. For example, if the name is reg.host instruction fifo 0, the instance number of this node is 0. The DMA FIFO must be of type Host to Target, with a data type of U64. To instantiate a DMA FIFO with the correct data type and correct settings, copy and paste a DMA FIFO from a sample project that uses this library and update its configuration as required.
  • reg.host read.go rcvd specifies whether the Register Bus host nodes read a value of TRUE on the reg.host read.data parameter as part of the handshaking protocol. The default value is FALSE. The reg.host read.go rcvd parameter is used during a read operation that was done using Read Register or Read Register Array in the Register Bus palette. When the Register Bus FPGA nodes complete the read operation, the Process node sets the go element of the reg.host read.data cluster to TRUE. The Register Bus host nodes wait until it reads this value before it reads the data returned by the data element of the reg.host read.data cluster. The host nodes set the reg.host read.go rcvd parameter to TRUE to tell the FPGA that it received the data. Then, the FPGA library sets the go element of the reg.host read.data parameter to FALSE, and finally, the Host library sets the reg.host read.go rcvd parameter to FALSE to end the transaction between the host and the FPGA for this register read operation. The Register Bus FPGA nodes wait until the reg.host read.go rcvd parameter is set to FALSE before processing the next register instruction. The reg.host read.go rcvd parameter must be wired to a control on the top-level FPGA node because this parameter must be accessible to the Register Bus host nodes from the Read/Write FPGA Control. The control must have a pre-defined name based on the value passed to the bus instance parameter of Open Session. The format of the name is reg.host read.go rcvd N, where N is the instance number of the Register Bus Host nodes and Register Bus FPGA nodes. For example, if the name is reg.host read.go rcvd 0, the instance number of this library is 0.
  • read completion specifies whether a register read operation is complete and provides the data from the register read to be returned to the host. This input is designed to be wired from a shift register inside a clock-driven loop or a feedback node. The value wired into the shift register inside the clock-driven loop or the feedback node can be obtained from the Read Completion Mux node of this library or the Registers node of another subsystem's FPGA library. read completion.data specifies the value read during the register read operation.
  • read completion.valid specifies whether the register read operation is complete and data is ready to be returned to the host.
  • ready for output specifies whether the downstream blocks are ready to accept a new register instruction. If you set this parameter to TRUE, the downstream blocks are ready to accept a new register instruction and this node provides a new register instruction, if available. If you set this parameter to FALSE, this node sets the valid element of the register instruction cluster to FALSE and holds any valid register instructions until you set the ready for output parameter to TRUE.

Output Parameters

  • reg.notify host.go indicates whether an instruction has been retrieved and processed by the Register Bus FPGA nodes. This parameter is used with the reg.notify host.go rcvd parameter as part of the handshaking protocol between the host and FPGA to return a notification to the host. The reg.notify host.go rcvd parameter is only used when the Register Bus host nodes request a notification by setting the wait until committed parameter to TRUE on Write Register or Write Register Array. In this case, when the FPGA library completes the write operation, Process sets this parameter to TRUE. The Register Bus host nodes wait until the node reads this value before it sets the reg.notify host.go rcvd parameter to TRUE to tell the FPGA that it received the notification. Then, the Register Bus FPGA nodes set the reg.notify host.go parameter to FALSE, and finally, the Register Bus host nodes set the reg.notify host.go rcvd parameter to FALSE to end the transaction between the host and the FPGA for this notification. The Register Bus FPGA nodes wait until the reg.notify host.go rcvd parameter is set to FALSE before processing the next register instruction. The reg.notify host.go parameter must be wired to an indicator on the top-level FPGA VI because it must be accessible to the Register Bus host nodes from Read/Write FPGA Control. The indicator must have a predefined name based on the value passed to the bus instance parameter of Open Session. The format of the name is reg.host read.data N, where N is the instance number of the Register Bus host nodes and Register Bus FPGA nodes. For example, if the name is reg.host read.data 0, the instance number of this library is 0.
  • reg.host read.data returns the data that is read during a register read operation. This parameter is used with the reg.host read.go rcvd parameter as part of the handshaking protocol between the host and FPGA to return this data to the host. The reg.host read.data parameter must be wired to an indicator on the top-level FPGA node because it must be accessible to the Register Bus host nodes from Read/Write FPGA Control. The indicator must have a pre-defined name based on the value passed to the bus instance parameter of Open Session. The format of the name is reg.host read.data N, where N is the instance number of the Register Bus host nodes and Register Bus FPGA nodes. For example, if the name is reg.read data 0, the instance number of this library is 0.
  • reg.host read.data.go indicates whether a read operation is complete and initiates the transaction of returning the data read to the host. When the FPGA nodes complete the read operation, the Process node sets this parameter to TRUE. The Register Bus host nodes wait until the node reads this value before it reads the data read in this register read operation. The Register Bus host nodes set the reg.host read.go rcvd parameter to TRUE to tell the FPGA that it received the data. Then, the Register Bus FPGA nodes sets this parameter to FALSE, and finally, the Register Bus host nodes sets the reg.host read.go rcvd parameter to FALSE to end the transaction between the host and the FPGA for this register read operation. The Register Bus FPGA nodes wait until you set the reg.host read.go rcvd parameter to FALSE before processing the next register instruction.
  • reg.host read.data.data returns the data read in this register read operation. When the go element of the reg.host read.data cluster is set to TRUE to initiate a transaction with the host, the data in the data element is valid. The data remains valid until the end of the transaction with the host and becomes invalid when the Register Bus host nodes change the value of the reg.host read.go rcvd parameter to FALSE.
  • register instruction specifies a read or write register instruction. Wire this parameter to the register instruction parameter of the Registers node on the FPGA VIs that are used with the Register Bus, such as the Waveform Sequencer FPGA library or the Multirecord Acquisition FPGA library.
  • register instruction.subsystem returns the destination subsystem for this register read or write operation.
  • register instruction.address returns the destination address in the specified subsystem for this register operation.
  • register instruction.data returns the data to be written to the specified register for a write operation.
  • register instruction.valid indicates whether there is a valid register read or write operation in the cluster. This parameter returns TRUE if there is a valid register read or write operation in the cluster, and returns FALSE if there is no valid register read or write operation in the cluster.
  • register instruction.read indicates whether the operation is for reading from, or writing to the specified register. This parameter returns TRUE if the operation is for reading from the specified register, and returns FALSE if the operation is for writing to the specified register.
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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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