Table Of Contents

Register Bus Nodes (Clock-Driven Logic)

Last Modified: September 9, 2016

Send register read and write instructions from your application on the host to the FPGA.

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Retrieves and decodes instructions from the host for reading and writing registers that are contained in the register banks of different subsystems on the FPGA, and controls the processing of each instruction.
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Routes an incoming read completion to the port that provided the register read instruction, when different instances of these nodes provide register instructions to the same destination subsystem. This node is designed to be used with the Register Instruction Arbiter node.
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Selects and returns one of multiple incoming read completions.
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Controls the flow of register instructions from different instances of the Register Bus FPGA nodes that may have the same destination subsystem.

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