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I16 to IQ (Clock-Driven Logic)

Last Modified: September 10, 2016

Converts each I16 into separate I and Q data in the fixed-point format. This node bundles the separate I and Q data into an I/Q data cluster, with an option to specify an overflow.

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I

I data represented as an I16.

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Q

Q data represented as an I16.

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overflow

A Boolean that specifies whether the I/Q data has overflowed.

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IQ data

A bundle of real and imaginary data.

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I

The bundled real data.

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Q

The bundled imaginary data.

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overflow

A Boolean that specifies whether the I/Q data has overflowed.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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