Table Of Contents

DSP Nodes (Clock-Driven Logic)

Last Modified: September 9, 2016

Design, implement, and analyze digital signal processor-based algorithms and systems.

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Digitally controls the I and Q signal levels.
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Digitally controls the I and Q offset.
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Applies a digital frequency shift to the I/Q data.
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Converts each I16 into separate I and Q data in the fixed-point format.
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Modifies the I/Q data to apply signal impairments.
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Converts a cluster of I/Q data into separate I and Q data in the fixed-point format, typecasts the separate I and Q data to convert them to I16s, and bundles the two I16s into a U32.
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Creates triggers based on configuration and power of the input data.
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Converts a cluster of I/Q data into separate I and Q data in the fixed-point format, and typecasts the separate I and Q data to convert them to I16s.
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Splits the U32 data parameter into two I16s and converts each I16 into separate I and Q data in the fixed-point format.

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