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Detect Falling Edge (Clock-Driven Logic)

Last Modified: September 10, 2016

Detects a transition from TRUE to FALSE on the input signal. Use Detect Falling Edge inside a Clock-Driven Loop.

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signal

The signal in which to detect a TRUE to FALSE transition.

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edge detected

A Boolean that indicates whether a TRUE to FALSE transition is detected on the input signal.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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