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ni579x FPGA Align 2 (Clock-Driven Logic)

Last Modified: September 10, 2016

Aligns the synchronization targets. You must align the synchronization targets before synchronizing a signal.

Host Align and FPGA Align provide the same quality of synchronization, but differ in requirements and versatility of operation. When using ni579x FPGA Align, the clock-driven loop (CDL) rate containing this node must be an integer multiple of the sync.cptr.Reference Clock rate, and the CDL clock must have a fixed phase relationship to the Reference Clock.

Each target performs its alignment independently, so FPGA Align does not require an FPGA I/O line. You can also use FPGA Align without host interaction. FPGA Align has 100% repeatability if-and-only-if the target-to-target phase relationship is low and does not change. When using ni579x Host Align, the CDL rate may be arbitrary, but still must have a fixed phase relationship to the other targets. The CPTR period may also be arbitrary. This alignment process is coordinated by the host, and requires an FPGA I/O line for orchestration. FPGA Align has 100% repeatability; if the hardware configuration remains constant, the level of synchronization remains constant as well.

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sync.resources

Identifies the Synchronization instance. Sync.resources is obtained from ni579x Create.

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sync.meas.Reference.Clock

The start signal. When using ni579x FPGA Align, the sync.meas.Reference Clock must be the same clock that the target's FPGA Clock is locked to. This is commonly PXI_Clk10.

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sync.resources 2

The synchronization instance is obtained from the create node.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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