Processes the FAM register operations sent from the host using the register bus.
A read or write register instruction. This parameter is usually obtained from the register instruction parameter of the Process node. The source of this parameter defines the Register Bus objects to which the Synchronization node is wired, and it is communicated from the host.
Indicates whether the register read operation is complete, and returns the data from the register read. Wire this parameter through either a shift register or a feedback node back to the read completion parameter on the Process node of the Register Bus.
A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
|True||The node is ready to accept new input data.|
|False||The node is not ready to accept new input data.|
Indicates when the FAM Registers interface is being accessed. To use the Register Bus signals, you must wait for this signal to be TRUE.
Configures the FAM Registers interface address for read or write data.
Indicates when the FAM Registers interface is being accessed.
Executes a Register Bus Read.
Returns the FAM Registers interface data to read from a Register Bus address.
Executes a Register Bus Write.
Configures the FAM Registers interface data to write to a Register Bus address.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices