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FAM Registers (Clock-Driven Logic)

Last Modified: September 10, 2016

Processes the FAM register operations sent from the host using the register bus.

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register instruction

A read or write register instruction. This parameter is usually obtained from the register instruction parameter of the Process node. The source of this parameter defines the Register Bus objects to which the Synchronization node is wired, and it is communicated from the host.

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read completion

Indicates whether the register read operation is complete, and returns the data from the register read. Wire this parameter through either a shift register or a feedback node back to the read completion parameter on the Process node of the Register Bus.

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ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
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Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

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IO Module\Register Bus Idle

Indicates when the FAM Registers interface is being accessed. To use the Register Bus signals, you must wait for this signal to be TRUE.

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Register Bus Address

Configures the FAM Registers interface address for read or write data.

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Register Bus Idle

Indicates when the FAM Registers interface is being accessed.

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Register Bus Read

Executes a Register Bus Read.

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Register Bus Read Data

Returns the FAM Registers interface data to read from a Register Bus address.

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Register Bus Write

Executes a Register Bus Write.

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Register Bus Write Data

Configures the FAM Registers interface data to write to a Register Bus address.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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