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Timing

Last Modified: May 17, 2017

The NI 7975R timing is controlled by various base clocks that you can use in your FPGA application.

The following figure shows the clock routing for the NI 7975R.

When LabVIEW code downloads to an FPGA target, the FPGA detects whether the 100 MHz oscillator clock is present, and if so, it configures the PLL to lock to the signal.
PXI_CLK10——10 MHz system reference clock. You can use this clock as a timebase for running your LabVIEW FPGA VI.
PXIe_DStarA—Trigger line that distributes high-speed, high-quality clock signals from the system timing slot to the peripherals. PXIe_DStarA has a configurable frequency for running your LabVIEW code on an FPGA target. You can drive PXIe_DStarA using a timing and synchronization device.
The PLL generates the following three clocks:
  • 40 MHz Onboard Clock—40 MHz base clock source. You can use this clock as a timebase for running your LabVIEW FPGA VI.

    The 40 MHz onboard clock is the default clock. This clock is generated from a PLL in the NI FlexRIO FPGA module. The PLL source is either PXIe_CLK100 or PXI_CLK10.

  • 100 MHz Clock—100 MHz base clock source. You can use this clock as a timebase for running code on your target FPGA. This clock is generated from a PLL in the NI FlexRIO FPGA module.
  • 200 MHz Clock—200 MHz base clock source. You can use this clock as a timebase for running code on your target FPGA. This clock is generated from a PLL in the NI FlexRIO FPGA module.
Adapter module socketed CLIP can include an external clock source, such as IO Module Clock 0 and IO Module Clock 1. The CLIP you select for your specific adapter module determines how the device uses this clock.

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