The period (in clocks) of the common periodic time reference (CPTR). The default value automatically sets the CPTR period to 10 MHz. The CPTR period controls the rate at which synchronized signals are realized. When you use FPGA Align, the CPTR period must be the same as the Reference Clock period. The sync.cptr.period must be set to the ratio of the clock-driven loop (CDL) rate that the Align node is in to the common reference rate. For example, the CPTR period must be 12 if using a 10 MHz Reference Clock, and the Data Clock for the CDL Clock (120 MHz/10 MHz). When you use Host Align, this value is configurable. The maximum value is 63. The minimum value for the sync.cptr.period must be big enough to ensure transmission across the sync.fpga io line. Refer to the specifications for the FPGA I/O line chosen. For example, if the FPGA I/O line has a maximum propagation delay of 50 ns, the minimum value is 6. Because the period of the 120 MHz Data Clock is ~8.333 ns, it would require 6 clock periods to exceed 50 ns. NI does not recommend changing the CPTR period while running. Alignment must be re-run if the CPTR period is changed.