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Simulates the specified Clock-Driven Logic (CDL) document on a host computer. This node simulates one clock period, or one iteration of a Clock-Driven Loop, per execution of the node.


Retaining Data between Executions

If you place this node in a loop, each execution of this node advances time within the simulation and updates stateful code, such as Feedback nodes, memory, or FIFOs, inside the CDL document. When you stop the host VI, the CDL document resets and the Run FPGA Simulation node does not carry over any state from the previous execution of the host VI to the next execution.