In addition to the default parameters of the Multirate Diagram node, the node also outputs a FIFO reference for each data port on the multirate diagram.
The Multirate Diagram node behaves differently in a VI targeted to an FPGA than in a VI targeted to a host. If you call a Multirate diagram from a VI targeted to an FPGA, the Multirate Diagram node outputs a FIFO reference for each port on the Multirate diagram. The Multirate diagram receives data from the FIFOs as a stream and returns data to the FIFOs as a stream. You can wire the FIFO references into a Clock-Driven Loop to send data between the Multirate diagram and the rest of the application. You must write to and read from the FIFOs to pass data to and from the Multirate diagram.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: Windows
FPGA: All devices (only within an FPGA Algorithm)
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