Performs Viterbi unquantized decoding on a convolutionally encoded bit stream using a custom generator matrix.
The number of trellis stages used in the Viterbi decoding process.
Default: 15
The unquantized BPSK demodulated soft symbol data.
The generator connection polynomial matrix that sets the convolutional feedforward node connections in octal format.
The convolutional node is modeled as a linear feedforward shift register arrangement consisting of k rows with K-1 shift registers per row, where k denotes the data word length and K denotes the constraint length. If a _{ ij } {0 ≤ i ≤ n-1, 0 ≤ j ≤ k-1} denotes a particular element in the generator matrix, the row index i corresponds to the convolutional node output y _{ i } that is affected by this element, while the column index j corresponds to the jth row in the k row shift register arrangement. Thus a _{ ij } specifies how the K bits in the jth row of the feedforward shift register matrix affects the ith output of the convolutional node.
For a rate of 2/3, the generator matrix is specified as follows:
$\left(\begin{array}{cc}100100& 011000\\ 011100& 101000\\ 110000& 010000\end{array}\right)=\left(\begin{array}{cc}44& 30\\ 34& 50\\ 60& 20\end{array}\right)$
The matrix on the right represents the elements in octal format. Zeros are padded at the end of the corresponding code generator sequences such that their total length is a multiple of three digits. The following diagram depicts the rate 2/3 convolutional node corresponding to the previously mentioned generator matrix, with a constraint length equal to 4. In the following diagram, D represents a shift register or memory element.
Here, y _{ i } ^{ j }, 0 ≤ j ≤ n-1 denotes the jth output of this node, in the ith instance.
Default: $\left(\begin{array}{c}5\\ 7\end{array}\right)$
The maximum number of encoded bits that can be affected by a single input bit. This value represents (1 + maximal memory order), where maximal memory order refers to the length of the longest shift register chain in the convolutional encoder.
Default: 3
The initial parent state for the decode operation. When reset? is set to TRUE, the trellis structure is set to this state, thereby initializing the Viterbi decoding operation. On the first call to this node, and thereafter when reset? is set to FALSE, the survivor state from the previous iteration is used to continue performing Viterbi decoding and this parameter is ignored.
Default: 0
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: no error
A Boolean that determines whether the internal state of the decoder is cleared.
TRUE | Clears any buffered bits from previous iterations. Also initializes the Viterbi algorithm to start decoding from initial state. The relationship of the length of output bit stream, L _{ out }, to the length of input bit stream, L _{ in }, is described by the following equation: L _{ out } = k × [floor(L _{ in }/n) - D] where k is the input data word length, n is the output data word length, and D is the decoder traceback depth in symbols. |
FALSE | Continues decoding from the previous iteration. The length of output bit stream is given by the following equation: L _{ out } = k × floor(L _{ in }/n). |
If the length of the encoded bit stream is L _{ in }, and reset? is set to TRUE, the Viterbi decoding algorithm (for a rate k/n code) returns a total of L _{ out } = k×[floor(L _{ in }/n)-D] decoded bits in a single iteration, implying that a total of k×D message bits are buffered inside the node. To recover the entire message of length k×floor[L _{ in }/n] in a single call to MT Convolutional Decoder with reset? set to TRUE, choose one of the following options:
Default: TRUE
Bit sequence decoded by this node.
The survivor state resulting from the Viterbi UnQuantized decision decoding operation after decoding the entire input bit stream.
Error information. The node produces this output according to standard error behavior.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
This site uses cookies to offer you a better browsing experience. Learn more about our privacy statement and cookie policy.