The Multirate Diagram node behaves differently in a VI targeted to an FPGA than in a VI targeted to a host. If you call a Multirate diagram from a VI targeted to an FPGA, the Multirate Diagram node outputs a FIFO reference for each port on the Multirate diagram. The Multirate diagram receives data from the FIFOs as a stream and returns data to the FIFOs as a stream. You can wire the FIFO references into a Clock-Driven Loop to send data between the Multirate diagram and the rest of the application. You must write to and read from the FIFOs to pass data to and from the Multirate diagram.
The following image shows a Top-Level FPGA VI that contains a Multirate Diagram integration node. The Context Help window in the image shows the names of the input and output terminals of the Multirate Diagram integration node.
In the Top-Level FPGA VI, the code inside the Clock-Driven Loop reads data from the host via the Data 1 In and Data 2 In FIFO constants. The Write FIFO nodes then send that data to the Stream In 1 and Stream In 2 ports on the Multirate diagram. The bottom section of code inside the Clock-Driven Loop reads data from the Multirate diagram and sends that data to the host via the Data Out FIFO constant.
Whenever enough data samples are available in the FIFOs that correspond to Stream In 1 and Stream In 2, the Multirate diagram consumes those samples and produces output samples. The Multirate diagram continues to process samples as long as the Top-Level FPGA VI executes.