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    Exports data from a Multirate Diagram to an FPGA VI using a FIFO.

    On a Multirate Diagram targeted to the host, an Output Port exports data directly to a host VI without using a FIFO.

    Use the Configure tab to set the buffer configuration for this port.

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    Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: All devices