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You can use multiple programming languages to develop your application. How you integrate pieces of code written in different languages into your overall application depends on the language and the target you are integrating the code into.

The following table provides integration details for each language in LabVIEW.

Language Integration Details
G

You can call a VI from the following source documents:

  • Host VI—Create a subVI node by dragging the VI from the Files pane onto the diagram.
  • FPGA VI—Create a subVI node by dragging the VI from the Files pane onto the diagram.

You can also place a VI within an FPGA IP container to use G algorithms on an FPGA. Placing a VI within an FPGA IP container enables additional features, but also limits the palette to nodes and data types supported on an FPGA. You can then move the FPGA IP container to an FPGA. When you drag FPGA IP from the Source Code palette category onto the diagram, LabVIEW encloses the FPGA IP in an integration node.

You can call an FPGA IP VI from the following source documents:

  • Host VI—Use an FPGA IP integration node to simulate your code before moving it to an FPGA.
  • FPGA VI—Use an FPGA IP integration node only inside a Clock-Driven Loop.
  • Multirate Diagram—Use an FPGA IP integration node.
  • FPGA IP VI—Create a subVI node by dragging the FPGA IP VI from the Files pane onto the diagram.
Multirate Dataflow

When you drag a Multirate Diagram from the Source Code palette category onto the diagram, LabVIEW encloses the Multirate Diagram in an integration node.

You can call a Multirate Diagram from the following source documents:

  • Host VI—Use a Multirate Diagram integration node to simulate your code before moving it to an FPGA.
  • FPGA VI—Use a Multirate Diagram integration node only outside of a Clock-Driven Loop. Pass data between a Multirate Diagram and the code inside a Clock-Driven Loop using FIFO references.
  • Multirate Diagram—Create a subMRD node by dragging the Multirate Diagram from the Files pane onto the diagram.
Clock-Driven Logic

You can call Clock-Driven Logic from the following source documents:

  • FPGA VI—Add Clock-Driven Logic directly to the diagram inside a Clock-Driven Loop, or create a subCDL node by dragging the Clock-Driven Logic document from the Files pane into a Clock-Driven Loop.
  • Clock-Driven Logic document—Create a subCDL node by dragging the Clock-Driven Logic document from the Files pane onto the diagram.
MathScript

You can integrate MathScript code only into a host VI. Use a MathScript Node to import existing MathScript code into your application or to develop your application using MathScript functionality.

C

You can integrate C code only into a host VI. Use a C Node to import existing C code into your application or to develop your application using C functionality.

Note  

You must target documents to the same location before you can call a document from another document. For example, a host VI can call other documents targeted only to the host, and an FPGA VI can call other documents targeted only to the same FPGA.