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When developing an FPGA IP algorithm, you should consider the performance you want the algorithm to achieve when it runs on the FPGA. Performance criteria for an FPGA IP algorithm include clock rate, throughput, latency, and the initiation interval.

  • Clock Rate—The clock rate determines the intended execution rate of the individual pieces of code on the diagram.
  • Throughput—The throughput, in MegaCalls/second, is the rate at which the FPGA can call, or provide new inputs to, an FPGA IP VI.
  • Latency—Latency is the number of clock cycles the FPGA requires between receiving inputs and providing outputs for one call of an FPGA IP VI.
  • Initiation Interval—The initiation interval is the number of clock cycles the FPGA requires before it can provide new inputs to an FPGA IP VI. The initiation interval is related to clock rate and throughput by the following equation:

    Initiation Interval = Clock Rate / Throughput

The following image provides a visual explanation of FPGA IP performance criteria. If the total elapsed time between the start of Call 1 and the end of Call 3 is one nanosecond, then the performance values are as follows:

  • Latency is 6 clock cycles.
  • Initiation interval is 2 clock cycles.