You can increase the throughput of FPGA IP code by simplifying the indexing logic for arrays in FPGA IP VIs.
When you compile FPGA code, the compiler looks for opportunities to increase parallelism and thereby increase the throughput of the code. In particular, the compiler easily recognizes the following indexing patterns and can make optimizations to process array data in parallel:
Refer to the following example sections for code that demonstrates these patterns.
When you compile the following code, the compiler analyzes the access pattern of the Coefficients - Weighted Average array and determines that each iteration of the loop depends on different subsets of the array. As a result, the compiler splits the array into these subsets that can be processed in parallel, and the FPGA IP VI achieves an initiation interval of one clock cycle. If the compiler did not make any optimizations for the parallel processing of array data, the initiation interval for this example would be four clock cycles because the presence of the Feedback Node would not allow a new sample to be processed until all loop iterations completed.
When you compile the following code, the compiler determines that Index Array reads elements sequentially from the array. Based on this information, the compiler can unroll the For Loops and implement memory more efficiently.