Memory resources might pass array data differently than you want to process it. For example, a DMA FIFO passes array data one element at a time. However, you might design your code to process all the array elements at once. You can use a simple FPGA IP VI to collect the array elements from the FIFO so you can process the elements together.
Complete the following steps to implement serial-to-parallel buffering and parallel-to-serial buffering in a top-level FPGA VI using a wire in a simple FPGA IP VI:
Create an FPGA IP VI that includes an array control wired to an array indicator, as shown in the following image.
Configure the FPGA IP VI so you can call it from a top-level FPGA VI.
From a top-level FPGA VI, call the FPGA IP VI in a Clock-Driven Loop. To place the FPGA IP VI on the diagram, drag it from the Source Code category in the Project Items palette. LabVIEW encases the FPGA IP VI in an integration node.
To implement parallel-to-serial buffering, configure the FPGA IP integration node to use standard mode for inputs and element-by-element mode for outputs. To implement serial-to-parallel buffering, configure the FPGA IP integration node to use element-by-element mode for inputs and standard mode for outputs.
In the following example, the top-level VI reads data serially from the host, reverses the data, and streams the resulting data serially back to the host.
- Parallel-to-serial buffering—Uses standard mode for inputs, element-by-element mode for outputs.
- Serial-to-parallel buffering—Uses element-by-element mode for inputs, standard mode for outputs.