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You can use an FPGA IP VI to implement a line buffer for window-based image processing, useful for Sobel Filters, convolution, and similar operations. This recommended design is optimized to achieve an initiation interval of one clock cycle, meaning one pixel sampling per cycle.

What to Use

What to Do

Create the following diagram to implement a line buffer for window-based image processing.

Customize the gray sections for your unique programming goals.

Initialize the window.
Incoming pixels occupy the bottom right-most slot in their window.
Read a column from the delay line.
Append a pixel to a column in the delay line.
Shift the window and add the new column.
Update the delay line with the new column.
Filter the image based on your application needs. This example demonstrates computing the median of the image.

When you use this code as an FPGA IP VI on the diagram in Clock-Driven Logic, set the array input and output modes to Element-by-element on the Configure tab. Using the element-by-element mode results in an initiation interval of one clock cycle.


  • If your initial interval is not what you expect, verify you set the input and output modes to Element-by-element. If you use the standard interface mode, the design processes an entire row of pixels at a time, resulting in an initiation interval equal to the number of pixels in the row.
  • You have to adapt this example to handle end-of-line or end-of-frame cases.