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FPGA IP algorithms require a certain amount of FPGA resources to execute. The following table summarizes factors that require greater utilization of a particular FPGA resource. For example, increasing the size of arrays in your algorithm requires greater use of Block RAM.

Resource Utilization Factors Block RAM DSP48 Flip-Flops LUTs
Increasing array size
Increasing multiply and multiply-accumulator operations
Increasing use of Boolean and Numeric nodes
Increasing use of Math nodes
Increasing clock rate
Increasing throughput
Note  

This table summarizes general trends. To develop a better sense of the resources your specific algorithm requires, use the FPGA Estimates button on the VI tab.

In addition to the factors listed in the table, increasing the complexity of your algorithm leads to greater utilization of all FPGA resources. Common design choices that result in more complex algorithms include a high number of nested loops and the use of wider data types such as 32-bit numbers versus 16-bit numbers.