When estimating FPGA IP resources from a top-level VI, keep the following considerations in mind:
- Directive permanence in a top-level VI—Performance directives, such as clock rate and throughput, persist for all calls of the FPGA IP VI when you set them through the top-level VI. This is not true for directives you set within the FPGA IP VI.
- Compilation time savings—Even if you estimated resources from within the FPGA IP VI, estimating them again from the top-level VI saves compilation time when you transfer your algorithm to hardware.
- Appropriate wiring for the interface mode—When you switch the interface mode from standard to element-by-element or vice-versa, any existing wires between the FPGA IP node and your input and output code break. Standard mode requires array data and element-by-element mode requires scalar data.