The performance directives of an FPGA IP VI are clock rate and throughput. Specifying these directives in LabVIEW instructs the compiler to find a hardware implementation for the FPGA IP VI that runs at the specified clock rate while meeting the specified throughput.
You can specify the directives for an FPGA IP VI in two locations:
Matching the clock rate of the FPGA IP VI to the clock rate of the Clock-Driven Loop that contains the FPGA IP VI is a recommended starting point. However, these clock rates do not have to match. Targeting a higher clock rate for the FPGA IP VI than the Clock-Driven Loop tends to increase the pipeline stages of the design, which in turn results in a higher achievable clock rate for the surrounding loop.