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The performance directives of an FPGA IP VI are clock rate and throughput. Specifying these directives in LabVIEW instructs the compiler to find a hardware implementation for the FPGA IP VI that runs at the specified clock rate while meeting the specified throughput.

You can specify the directives for an FPGA IP VI in two locations:

  • When you use an FPGA IP node within a top-level VI, you select the node and specify the directives in the Configure tab.

    Matching the clock rate of the FPGA IP VI to the clock rate of the Clock-Driven Loop that contains the FPGA IP VI is a recommended starting point. However, these clock rates do not have to match. Targeting a higher clock rate for the FPGA IP VI than the Clock-Driven Loop tends to increase the pipeline stages of the design, which in turn results in a higher achievable clock rate for the surrounding loop.

  • When you are on the panel or diagram of an FPGA IP VI, you click FPGA Estimates on the VI tab to specify the directives.

The compiler does not guarantee a hardware implementation with the exact clock rate and throughput rate that you specify in the directives. For this reason, it is important to estimate an FPGA IP VI to determine if the design meets the performance requirements.