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FPGA IP allows you to easily create and transfer algorithms to an FPGA target. FPGA IP VIs are VI Diagrams stored within a container in SystemDesigner called an FPGA IP container.

FPGA IP containers separate your algorithms from other parts of your application, such as Clock-Driven Logic or Multirate Diagram documents.

The nodes available for FPGA IP VIs represent a subset of G Dataflow nodes focused on algorithmic code. During FPGA IP development, the LabVIEW editor displays warnings if aspects of your algorithms will not function on the FPGA target. It also provides tools that help you estimate the FPGA resources your algorithms require.